1. Field of the Invention
The present invention relates to an electrical device having an output transistor for limiting an input current to produce an output current and a bypass capacitor connected to the output side of the output transistor.
2. Description of the Prior Art
Since its debut some time ago, the USB (universal serial bus) has been receiving much attention as an interface bus for connecting a host computer, such as a personal computer, to a peripheral device, such as a floppy disk drive, printer, scanner, or the like. Peripheral devices equipped with a USB (hereinafter such devices will be referred to as xe2x80x9cUSB devicesxe2x80x9d) make it possible to use a single unified interface for a plurality of peripheral devices that have conventionally been requiring different interfaces.
A USB device is connected to a host computer by way of a USB cable. For easy connection and convenience, the USB cable includes not only signal lines by way of which signals are exchanged between the USB device and the host computer, but also power supply lines by way of which electric power is supplied from the host computer to the USB device.
Moreover, the USB device is equipped with a high side switch circuit for making xe2x80x9csofterxe2x80x9d (less abrupt) the rising of the rush current that occurs when the USB device is plugged into the host computer, and thus the power supply lines of the USB cable are connected through the high side switch circuit to the internal circuits of the USB device. The high side switch circuit is configured as a current limiter that limits the supply current supplied from the host computer to a predetermined level before it is fed to the internal circuits.
FIG. 10 is a circuit diagram showing an example of the configuration of a conventional high side switch circuit. As this figure shows, the high side switch circuit 10xe2x80x2 is provided with an output transistor Q1 that limits the supply current supplied from outside the device to produce an output current to be output to the internal circuits of the device. The figure shows an example in which a P-channel MOS transistor is used as the output transistor Q1.
The supply current fed from outside the device is fed in via an input terminal T1. The input terminal T1 is connected through a resistor R1 to the source (S) of the transistor Q1, and is also connected through serially connected resistors R2 and R3 and then through a constant-current source 11 to ground. The current that is to be fed to the internal circuits of the device is fed out via an output terminal T2. The output terminal T2 is connected to the drain (D) of the transistor Q1, and is also connected through a bypass capacitor C1 to ground.
Moreover, the high side switch circuit 10xe2x80x2 is provided with an operational amplifier A1 as a means for controlling the gate voltage of the transistor Q1. The non-inverting input terminal (+) of the operational amplifier A1 is connected to the node between the resistors R2 and R3, and its inverting input terminal (xe2x88x92) is connected to the source (S) of the transistor Q1. The output terminal of the operational amplifier A1 is connected to the gate (G) of the transistor Q1.
Now, how this high side switch circuit 10xe2x80x2 configured as described above operates will be described. The operational amplifier A1 amplifies the voltage difference between the reference voltage Vref fed to its non-inverting input terminal (+) and the comparison voltage Vadj fed to its inverting input terminal (xe2x88x92), and thereby produces the gate voltage of the transistor Q1.
For example, when a large current flows through the transistor Q1, the voltage drop across the resistor R1 becomes greater. Thus, the comparison voltage Vadj drops, and the output voltage of the operational amplifier A1 becomes higher. As a result, the voltage difference between the gate and source of the transistor Q1 becomes smaller, and thus the transistor Q1 now permits only a smaller current to flow through it. By contrast, when the current that flows through the transistor Q1 becomes smaller, and thus the comparison voltage Vadj becomes higher, the output voltage of the operational amplifier A1 becomes lower. As a result, the voltage difference between the gate and source of the transistor Q1 becomes greater, and thus the transistor Q1 now permits a larger current to flow through it.
In this way, the high side switch circuit 10xe2x80x2 is a circuit that limits the output current Iout that flows through the transistor Q1 in such a way that the comparison voltage Vadj is kept equal to the predetermined reference voltage Vref. In this high side switch circuit 10xe2x80x2 configured as described above, setting the reference voltage Vref higher results in making the target value of the output current Iout smaller and, by contrast, setting the reference voltage Vref lower results in making the target value of the output current Iout greater. Conventionally, the reference voltage Vref is fixed at a voltage determined on the basis of the ultimate target value of the output current Iout to be fed to the internal circuits of the device.
FIG. 11 is a time chart showing the behavior of the input voltage Vin and the output current Iout in the high side switch circuit 10xe2x80x2. As solid lines in this figure indicate, when an input voltage Vin is applied to the input terminal T1 of the high side switch circuit 10xe2x80x2, an output current Iout starts flowing through the bypass capacitor C1. Here, the rising of the output current Iout that charges the bypass capacitor C1 is made softer to a certain degree by the high side switch circuit 10xe2x80x2.
The peak value of the current that charges the bypass capacitor C1 and the time needed to charge it are determined by the capacitance of the bypass capacitor C1 and the reference voltage Vref of the high side switch circuit 10xe2x80x2 (i.e. the target value of the output current Iout). In FIG. 11, what the solid lines indicate is the behavior observed when the bypass capacitor C1 is the only load that is connected to the output terminal T2, and accordingly, when the charging of the bypass capacitor C1 is complete, the output current Iout drops to zero. In a case where another load circuit is connected to the output terminal T2, however, a current commensurate with the load continues to flow even after the completion of the charging of the bypass capacitor C1 (as a dash-and-dot line in the figure indicates).
The high side switch circuit 10xe2x80x2 configured as described above does serve, indeed, to limit the output current Iout fed out via the output terminal T2 through feedback control as described above and thereby make softer to a certain degree the rush current that occurs when the USB device is plugged into the host computer. Thus, it is possible to prevent to a certain extent the power supply circuit provided in the host computer from being overloaded. In addition, the output current Iout from the high side switch circuit 10xe2x80x2 is first accumulated in the bypass capacitor C1 before it is fed out. This helps make smooth and reduce the noise components in the current that is fed to the internal circuits of the USB device.
However, in the conventional high side switch circuit 10xe2x80x2, the bypass capacitor C1 is given a fixed capacitance that is so set that the peak value of the current that charges it and the time needed to charge it comply with the USB standard and the specifications of the ICs used internally. That is, it is impossible to adjust the waveform of the current that charges the bypass capacitor C1 according to the power supply performance of the power supply circuit provided in the host computer, the characteristics of the USB cable, and other factors (i.e. to adjust it, for example, in such a way that the peak value of the current that charges the bypass capacitor C1 and the time needed to charge it comply with the USB standard and the IC specifications, and simultaneously that the output current Iout rises as softly as possible).
An object of the present invention is to provide an electrical device that has an output transistor for limiting an input current fed from outside to produce an output current and a bypass capacitor connected to the output side of the output transistor but that nevertheless permits the waveform of the current that charges the bypass capacitor to be adjusted without varying the capacitance thereof.
To achieve the above object, according to the present invention, an electrical device is provided with: an output transistor for limiting an input current fed from outside the electrical device to produce an output current to be fed to inside the electrical device; an output controller for controlling the current limiting operation of the output transistor; and a bypass capacitor connected to the output side of the output transistor. Here, the waveform of the current that charges the bypass capacitor is adjusted by varying the limit value of the output current without varying the capacitance of the bypass capacitor.